Home→Job Titles→SR. PRINCIPAL FPGA/ASIC DESIGN ENGINEER

SR. PRINCIPAL FPGA/ASIC DESIGN ENGINEER H1B Salary Data

FY2019 – FY2025 • 2 employers • Official DOL Data

$197K

Median Salary

Total Filings

$180K–$215K

Middle 50%

Employers

P10: $170KP25: $180KMedian: $197KP75: $215KP90: $277K

Top Paying Companies

RED DIGITAL CINEMA, INC.

$277K

2 filings

RED DIGITAL CINEMA, LLC

$180K

8 filings

Top Cities

Thousand Oaks, CA

$230K

16 filings

Thousand Oaks, CALIFORNIA

$171K

12 filings

Irvine, CA

$143K

6 filings

Irvine, CALIFORNIA

$159K

5 filings

Foothill Ranch, CA

$169K

2 filings

San Jose, CA

$215K

2 filings

Austin, TEXAS

$153K

1 filings

SR. PRINCIPAL FPGA/ASIC DESIGN ENGINEER Salary Trend by Year

FY2019

$170K

2 filings

FY2021

$180K

3 filings

FY2022

$215K

3 filings

FY2025

$277K

2 filings