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LEAD ASIC DESIGN VERIFICATION ENGINEER (ASIC DV ENGR) H1B Salary Data

FY2015 – FY2018 • 1 employers • Official DOL Data

$130K

Median Salary

Total Filings

$110K–$135K

Middle 50%

Employers

P10: $110KP25: $110KMedian: $130KP75: $135KP90: $147K

Top Paying Companies

SMARTPLAY, INC.

$130K

53 filings

Top Cities

San Jose, CA

$125K

301 filings

San Diego, CA

$110K

115 filings

Santa Clara, CA

$135K

36 filings

Hillsboro, OR

$125K

16 filings

Austin, TX

$130K

13 filings

Mountain View, CA

$145K

11 filings

Sunnyvale, CA

$120K

9 filings

Boxborough, MA

$115K

8 filings

Irvine, CA

$137K

LEAD ASIC DESIGN VERIFICATION ENGINEER (ASIC DV ENGR) Salary Trend by Year

FY2015

$130K

42 filings

FY2016

$115K

8 filings

FY2017

$110K

2 filings

FY2018

$125K

1 filings